Embodiments of the invention relate to a LCD (liquid crystal display) driving device.
These days, TFT-LCDs (thin film transistor liquid crystal displays) have become the main flat panel displays and also have been developing towards large sizes and high resolutions. With the size of a TFT-LCD becoming ever larger, the gate scanning lines and the data signal lines in the TFT-LCD become ever longer. This gives rise to ever larger resistance of the gate scanning lines and the data signal lines; and higher resolution causes more intersecting and overlapping areas between the gate scanning lines and the data signal lines, which increases the parasitic capacitance for each signal line.
FIG. 1 is a schematic view showing the configuration of a conventional TFT liquid crystal display device. As shown in FIG. 1, across the pixel region of the TFT-LCD device, the horizontal gate scanning lines G and the vertical data signal lines D are arranged into a grid, each square in the grid represents a pixel, a thin film transistor T for controlling operation of the corresponding pixel is formed at each of intersections of the data signal lines D and the gate scanning lines G. Among these lines, the gate line preceding the first gate scanning line G is a redundant gate line (the gate line at the very top as shown in FIG. 1) for testing; and the data line succeeding the last data signal line D is a redundant data line (the data line at the very right as shown in FIG. 1) for testing. A data driving chip supplies data signals to the data signal lines D, through which the data signals are transferred to each pixel row in the pixel region. The gate driving chip controls the gate scanning lines G and supplies scanning signals to the gate scanning lines G row-by-row, so that the pixels in the pixel region can be switched on row-by-row through the thin film transistors, and thus the data signals from the data signal lines D can be transferred to pixels through the thin film transistors.
FIG. 2 is a schematic view showing the gate scanning signal outputted from the beginning of a gate scanning line (the portion of a gate scanning at the very left as shown in FIG. 1) of a conventional TFT-LCD. FIG. 3 is a schematic view showing the gate scanning signal outputted from the end of the gate scanning line (the portion of a gate scanning at the very right as shown in FIG. 1) of the conventional TFT-LCD. In the drawings, Gn stands for the nth gate scanning line. As shown in FIG. 2, the pixels are scanned row by row (or line by line). A GOE (Gate Open Enable) slot is kept between the high levels of each pair of neighboring data scanning lines. The width of the GOE slot equals the time delay caused by the product RC of the resistance R of the gate signal lines and the parasitic capacitance C caused by the overlapping areas between the signal lines so as to avoid the problem of signal interfering due to the RC time delay. As shown in FIG. 3, the gate scanning signal output from the end of each gate scanning line deforms, mainly due to the RC time delay.
With a certain resolution and scanning frequency, pixels of each row have a fixed-value scanning time. However, if the RC time delay becomes larger, the GOE slot requires larger margin, which leads to shorter charging time for the pixels. When the RC time delay reaches a threshold, the gate scanning signal causes the charging efficiency not to meet the requirement, which adversely affect the display quality of a TFT-LCD. In the same time, as the RC time delay becomes larger, the gate scanning signal of each row has a longer descending curve when it drops from the high level to the low one; as a result, the pixels have different voltage offsets at the left and right ends in a TFT-LCD, which leads to inhomogeneous display quality and thus causes display flicking.